1. Technical Field
The present invention relates to phase detection circuitry, and, more particularly, to a parallel sampling phase detector with linear output response for use, for example, in data recovery applications.
2. Discussion of the Related Art
There has been much investigation in the area of high bit rate transmitting/receiving circuitry, owing in no small part to the demand for increased bandwidth by the communications industry. In response, organizations such as the IEEE have proposed serial data communications standards with data rates in the Gigabit per second range. To eliminate the need for a separate conductor or optical fiber link carrying a companion clock signal, the above-noted serial communications standards generally call for the timing or clock information to be embedded in the data transmission itself. To insure proper transmission of timing information, it is conventional to require, in the data bitstream, a minimum number of transitions per unit time. To this end, various encoding schemes have been developed (e.g., 8B10B, which defines a 10-bit data word), that transmit a sufficient number of transitions to insure recovery of timing at the far end.
With this background, it has been conventional practice for high speed data recovery systems to use a high frequency voltage-controlled oscillator (VCO) having a frequency substantially equal to the transmission bit rate (line bit rate). Conventional phase detectors, charge pump/loop filters, and VCOs are used to extract the embedded clock from the incoming data stream, and generate a "clean" clock signal operating at the incoming data bit rate. The "clean" clock is used to synchronize the sampling of the incoming data. The sampled data, which is recovered, conventionally, in a serial fashion (i.e., just like the incoming data stream), is then converted using a serial-to-parallel conversion circuit to produce an n-bit data word.
A problem with the foregoing approach, especially as the incoming data bit rate increases into the high frequency (e.g., greater than 1 Gigabit per second range) is that such a system requires a very high frequency VCO (producing a clock signal operating at the line bit rate), and an extremely fast phase detector. This results in relatively high power consumption. In some cases, the called-for bit rate is so high that it may be impractical to generate at all using some (e.g., standard CMOS) semiconductor processes. Moreover, to implement the serial-to-parallel conversion, fast shift registers must be used, which further increase the already relatively high power consumption.
Another approach in the art has been to use a VCO generating multiple phases, each at a frequency lower than the line bit rate, and use these VCO phases with multiple phase detectors. In this approach, fixed pulsewidth "pump up" and "pump down" control pulses are generated which, as is well known, are filtered and used to generate a control signal which varies the output frequency of the VCO. A disadvantage with this approach is that the fixed pulsewidth "pump up" and "pump down" signals result in an increased sensitivity to duty cycle distortion (i.e., a "dead zone" is caused by the fixed pulsewidths which do not provide a linear indication of the phase difference between the VCO clocks and the incoming data stream). In addition, use of the fixed pulsewidth "pump up" and "pump down" signals result in data dependent phase jitter.
Thus, there is a need to provide an improved system for phase detection and/or data recovery that minimizes one or more of the problems as described above.